1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to configurations and methods implemented with trench nano-tubes with trench sidewalls covered with doped epitaxial layer and then filled with insulative material for manufacturing flexibly scalable charge balanced semiconductor power devices with simplified manufacturing processes and achieving improved breakdown voltage and significantly reduced resistance.
2. Description of the Prior Art
Even though there have been many patented disclosures and published technical papers related to semiconductor devices with vertical super junction structure to achieve improved electrical characteristics, those who are involved in the fields of designing and manufacturing the super-junction semiconductor devices are still confronted with technical difficulties and manufacturability limitations. Specifically, the most common super junction devices include the metal oxide semiconductor field effect transistor (MOSFET) and insulated gate bipolar transistor devices and many patented disclosures are published for these devices including U.S. Pat. Nos. 5,438,215, 5,216,275, 4,754,310, 6,828,631. Fujihira further discloses configurations of the vertical super junction devices in the publication “Theory of Semiconductor Super Junction Devices” (Japan Journal of Applied Physics Vol. 36, October 1997 PP 6254-6262). Specifically, FIG. 2A in Fujihira's paper shows a vertical trench MOSFET super junction device published by Fujihira, shown here as FIG. 1A. Fujihira also discloses in U.S. Pat. No. 6,097,063 a vertical semiconductor device having a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively. U.S. Pat. No. 6,608,350 discloses a vertical super junction device implemented with layers of a dielectric material to fill in the trenches and U.S. Pat. No. 5,981,996 discloses a vertical trench MISFET device as that shown in FIG. 1B.
However, the configurations and operational characteristics of the super junction devices as disclosed in these patented and published disclosures still encounter technical limitations thus restricting the practical usefulness of these devices. The difficulties and limitations of the conventional super junction devices include the problems and technical issues involved in filling the deep trenches, the size limitation of the nano tubes formed in the trenches, the preservation of charge balance at the mesa areas adjacent to the termination area, poor unclamped inductive switching (UIS) capability of the super-junction devices, oscillation issue of the super junction power devices, high production cost of super junction devices due to slow epitaxial growth rate, inter-diffusions of the N and P impurities in the superjunction structure at high temperatures, difficulties of integrating different devices on a same chip, and large termination area for high voltage applications.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing method in forming the power devices such that the above discussed problems and limitations can be resolved.